Low-Power Design by Hazard Filtering

Abstract Before signals of a digital circuit reach steady state gates can have multiple transitions Since the power is dissipated in a CMOS circuit mainly due to transitions the extra transitions increase power consump tion These transitions are the hazard pulses generated by logic gates when signals arrive by paths of varying de lays The maximum width of a hazard pulse produced by a gate is the maximum di erence between the delays of inci dent paths which is generally much smaller than the clock period We propose suppression of hazard pulses by in creasing the delays of gates where hazards could have been generated Thus a hazard ltering gate has a delay which is at least as much as the di erential delay of its input paths We give examples to illustrate the novel technique and also indicate that the overall reduction in the circuit speed may not be too much with proper sizing of transis tors while there can be a signi cant reduction in power consumption